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Sr. Field Applications Engineer, CA
Job Location :

Sunnyvale, or San Diego, CA
United States





Real Intent
990 Almanor Ave
Suite 220
Sunnyvale, CA 94085
United States
Employment term : Full Time
Travel : Moderate 25% to 50%
Job level : Mid Level 2-6 yrs.
Work Authorization :
  • Authorized to work

    If you are looking for an exciting career move, with a successful start up in the field of Electronic Design Automation, Real Intent is looking for new applications engineers to join it’s team! Come work with a team of top notch experts in the field of clock verification, RTL sign off and automatic formal. We offer an exciting work environment with competitive compensation and benefits.


    The Senior FAE is a vital member of the Applications Engineering Team. The Senior FAE works with customers to provide superb technical consultation and maintain strong customer relationships. The position has primary responsibility for the technical success of software evaluations at prospective customers as well as tool deployment in existing accounts. Candidates must be able to effectively work with Engineering and Marketing departments to define software improvements, address market opportunities, and resolve customer issues with software tools.


    • BSEE or equivalent plus 5-8 years of experience or MSEE with 3-5 years experience in digital design, hardware verification, or applications engineering, with a proven track record for customer satisfaction.
    • Detailed working knowledge of Verilog and/or VHDL. SystemVerilog familiarity required, working knowledge a plus.
    • Excellent communication and technical presentation skills, both verbal and written
    • A self-starter with a history of driving projects to completion under tight schedules
    • Hands-on, technical in-depth experience in at least two of the following areas:
      • Asynchronous clock domain crossing verification on large SoC designs
      • Current commercial hardware RTL linting technologies, including detailed knowledge of rule sets
      • Hardware static timing analysis (STA) / timing closure flows involving SDC timing files
      • Assertion-based formal property hardware verification
      • Testbench-driven hardware simulation flows
    • Up to 25% travel required, including international

    Real Intent Profile:

    Real Intent is the leading provider of EDA software to accelerate RTL Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.


    We have more than 40 major semiconductor companies using our products on a worldwide basis, including some of the largest companies developing ICs for mobile, networking, telecommunication and display graphics, among other applications.

    We place high priority on customer support and have excellent customer references.

    Real Intent has sales offices in the USA and Japan, and distributors in Europe, India, Israel, Korea and Taiwan.


    Real Intent offers two product families – Ascent for early functional verification before simulation or synthesis; and Meridian for advanced sign-off verification not possible with simulation or static timing analysis.

    Ascent for Early Functional Verification

    Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. It includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.

    Ascent Implied Intent Verification (IIV) is an early functional verification tool that automatically finds elusive bugs in RTL without the need for writing assertions or testbenches. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent IIV can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation.

    Ascent X-Verification System (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.

    Meridian for Advanced Sign-off Verification

    Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. With giga-gate capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.

    Meridian Constraints is the most comprehensive constraint management solution in the market. It offers high-performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of the implementation flow.

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