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Sr. Field Applications Engineer
Job Location :
990 Almanor Ave
Suite 220
Sunnyvale, CA 94085
United States





Real Intent
990 Almanor Ave
Suite 220
Sunnyvale, CA 94085
United States
Employment term : Full Time
Travel : Moderate 25% to 50%
Job level : Mid Level 2-6 yrs.
Work Authorization :
  • Authorized to work

    The FAE is a vital member of the Sales team. The FAE influences and motivates customers to purchase Real Intent tools by providing superb technical sales support and maintaining strong customer relationships.  The FAE position has primary responsibility for the technical success of software evaluations at prospective customers as well as tool deployment in post-sales accounts.  Candidates must be able to effectively work with Engineering and Marketing departments to define software improvements, address market opportunities, and resolve customer issues with software tools.


    • BSEE or equivalent plus 5-8 years of experience or MSEE with 3-5 years experience in digital design, hardware verification, or applications engineering, with a proven track record or customer satisfaction.
    • Detailed working knowledge of Verilog and/or VHDL.  SystemVerilog familiarity required, working knowledge a plus.
    • Excellent communication and technical presentation skills, both verbal and written
    • A self-starter with a history of driving projects to completion under tight schedules
    • Hands-on, technical in-depth experience in at least two of the following areas:
      • Asynchronous clock domain crossing verification on large SoC designs
      • Current commercial hardware linting technologies, including detailed knowledge of rule sets
      • Hardware timing analysis / timing closure flows involving SDC timing files
      • Assertion-based formal property hardware verification
      • Testbench-driven hardware simulation flows
    • Up to 25% travel required, including international

    Real Intent Profile:

    Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of electronic designs.

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