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Real Intent

990 Almanor Ave
Suite 220
Sunnyvale, CA 94085
United States

Profile :

Real Intent is the leading provider of EDA software to accelerate RTL Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.

COMPANY SUCCESS

We have more than 40 major semiconductor companies using our products on a worldwide basis, including some of the largest companies developing ICs for mobile, networking, telecommunication and display graphics, among other applications.

We place high priority on customer support and have excellent customer references.

Real Intent has sales offices in the USA and Japan, and distributors in Europe, India, Israel, Korea and Taiwan.

PRODUCTS

Real Intent offers two product families – Ascent for early functional verification before simulation or synthesis; and Meridian for advanced sign-off verification not possible with simulation or static timing analysis.

Ascent for Early Functional Verification

Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. It includes smart rules that perform syntax and semantic checks for today’s complex System-on-Chip (SoC) designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.

Ascent Implied Intent Verification (IIV) is an early functional verification tool that automatically finds elusive bugs in RTL without the need for writing assertions or testbenches. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis. Ascent IIV can improve verification efficiency substantially and detect up to 50% of design functional errors prior to testbench development and simulation.

Ascent X-Verification System (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.

Meridian for Advanced Sign-off Verification

Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. With giga-gate capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.

Meridian Constraints is the most comprehensive constraint management solution in the market. It offers high-performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of the implementation flow.




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