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Listed
07/Jul/17

USA, California

SENIOR DDR/VIP DEVELOPER    Valley   #4915   This exciting Start-up with development teams in The Valley and Taiwan seeks a Manager/Developer...   Requirements   Hands-on Sr SW Developer/Manager   Hands om Strong coder in System Verilog and strong in UVM   Has worked specifically in Memory design- owned memory controller on the SOC  DDR4   Verification IP experience a plus, the more Senior.the better...a person that knows engineering …
Listed
07/Jul/17

USA, California

FAE      Front-End    Valley  #4101    This international successful Start-Up needs an FAE to represent them in the Valley. Most of the Top 10 IDM’s (Broadcom, Qualcomm, Fujitsu, ….) are customers and they have customers and support, worldwide.     Required Skills  Logic Synthesis, RTL Design, Verification; DFT is a plus Verilog, System Verilog and Tcl   Strong customer facing skills, good with benchmarks, demos …
Listed
12/Jun/17

USA, Florida

Company: Rulon …
Listed
17/May/17

USA, California

LVS  PEX DESIGN ENGINEERS    SILICON VALLEY  #4091   This well respected, Industry-Leading company is in search of a Senior Developer for layout-versus-schematic (LVS), electrical rule checking (ERC), and layout-parasitic-extraction (PEX), and other post layout simulation flows to be utilized in wide ranging CMOS technology nodes including FinFET, FDSOI, Bulk, SOI, RF, mm-wave.    Required Responsibilities:  Development of …
Listed
17/May/17

USA, California

LVS for PDK Design Engineer   SILICON VALLEY or NORTHEAST  #4095   This well respected, Industry-Leading company is in search of a Senior Developer for Join the Process Design Kit (PDK) Team to develop layout-versus-schematic (LVS) verification software. In this role you will develop Mentor’s Calibre code, used to compare schematic and layout values.    Primary Responsibilities: As an LVS developer, you develop Calibre LVS code for CMOS …


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