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Design Engineers PDK Parameterized Cells ( P-CELLS) SILICON VALLEY
Job Location :
San Jose, CA 95119
United States





EDA Careers
San Jose, CA 95119
United States
Employment term : Full Time
Degree : Masters
Travel : None
Job level : Senior Level 7+ yrs.
Work Authorization :
  • Authorized to work
  • USA: Citizen
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  • Design Engineers PDK Parameterized Cells ( P-CELLS)  SILICON VALLEY   REQ# 4093

    This very well-known and well respected Industry-Leading company, is in search of a Senior Developer for their Advanced Node PDK/Library team. The right Candidate will be responsible for developing design components for advanced node Process Design Kits (PDK). This position will give the right-motivated person the opportunity to contribute, grow, and collaborate with colleagues in the larger Design Enablement organization and have a direct impact on the Company’s success.  

    Primary Responsibilities:

    • Develop and maintain cells in the PDK library for each supported device…
      • MaskLayout, Schematic, SchematicSymbol views
        • parameterized or not…One or more levels of hierarchy
      • CDF
        • Model parameters and netlist configuration and procedures to support Spice simulation and LVS compare
        • Layout parameters to facilitate and boost physical design productivity
        • Callbacks to validate values, calculate and update secondary parameters
      • Connectivity, properties, entries in configuration files, etc. to fully enable custom/analog flows
    • Ensure components conform to foundry rules and specifications and pass quality criteria
      • Perform physical verification: DRC, LVS
      • Validate components through design flow
    • Author and  review release notes, user guides and other documentation
    • Develop, promote and exercise best practices and engage in continuous improvement efforts
      • Revision control, configuration management, and defect tracking
      • Build and test automation
      • Coding standards, code library, and peer code review
      • Document, and mentor

    Required Qualifications

    • Bachelor’s in electrical engineering, microelectronics or equivalent
    • 5 years of relevant experience, 3 years with Master’s, or a PhD 
    • Solid understanding of semiconductor processes, devices and their layout
    • Experience with custom/analog design flows with Cadence/Virtuoso
    • Proficiency in Cadence SKILL programming language and API: db, dd, rod, cdf, tech, etc.
    • Experience developing PDK library components for custom/analog design flows
    • Experience running  physical verification tools for DRC and LVS and interpreting results
    • Proficiency in scripting languages: Python, TCL, Shell, or Perl

    Additional Preferred Qualifications:

    • Experience with advanced technology nodes and multi patterning
    • Experience running Mentor/Calibre physical verification tools for DRC and LVS
    • Proficiency in Cadence SKILL++ and PAS
    • Experience developing fluid guard rings
    • Experience developing PyCells
    • Excellent technical problem solving skills
    • Outstanding communication skills – both written and verbal
    • Good attitude and interpersonal skills
    • Self-motivated, resourceful, shows initiative 

    Send resume to Apply Here then call 305-598-2222

    EDA Careers Profile:

    EDA-CAREERS is a unique company in the world of recruiting. With over 15 years in recruiting exclusively in the EDA/Semiconductor industry, we pride ourselves on our relationships. We WORK to help find the best fits for our companies and the best opportunities for our candidates. In effect, we become PARTNERS, so that both the candidate and the company process goes smoothly from beginning to end. That is why we have worked with over One Hundred companies in EDA, and placed such a broad array of candidates.  We do it all...R&D, AE's, Sales and Marketing.  We help virtually every level of talent and work Globally.

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