Microchip has an opportunity for a Principal ASIC Implementation Engineer at our office in Portland Oregon. As a key member of Microchip's ASIC Implementation team, the successful candidate will take responsibility for a team of engineers to execute Microchip's ASIC development methodologies with a focus on top-level timing closure and/or synthesis. They will coordinate the analysis and distribution of relevant timing information to sub-block/subsystem implementation engineers, as well as the Design and DFT groups.
Working knowledge of system Verilog design and verification for common IP, top-level DFT insertion, macro level test structures for high-performance devices is essential. The successful candidate will work closely with our internal and external customers to support them through Microchip's Chip development flow. They will also work with other Microchip groups across disciplines (CAD, Packaging, Mixed Signal, Operations, Layout) to facilitate the successful completion of the IC. Microchip's Principal Engineers lead, manage and mentor engineers to ensure that they understand and adhere to flows using state-of-the art tools to build large and complex SOCs/ASICs.
- Develop and execute implementation plans to synthesize, implement Design for Test, and/or close timing on complex digital integrated circuits at the block, subsystem or device level (1M to 1000M+ gates), which are coded in VHDL/Verilog/System Verilog.
- Use metric-driven techniques to help ensure first-pass working silicon and provide regular, meaningful progress reports.
- Create, enhance, and maintain synthesis, DFT, and Static Timing scripts to establish or update best-in-class methodologies.
- Analyze log and report files to ensure tools are properly configured to provide accurate results and make necessary adjustments to ensure that the manufactured device will function according to the design specification.
- Mentor Senior/Junior team members and contractors on Chip-level and Macro-level ASIC design and implementation flows and processes.
- Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems.
- Provide technical support for internal and external ASIC customers to ensure the ASIC projects are successful as per the development plans.
- Take responsibility for a team of engineers of varied experience and lead them to the successful implementation of a IC design within schedule constraints.
- BSEE with 10-12 years of ASIC development experience in a fast-paced environment.
- Design and Synthesis experience in high performance design (high speed / low power).
- State of the art knowledge of semi-custom design implementation tools.
- Experience with tools and methodologies for synthesis, hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization, and ECOs.
- Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, 'physical aware' synthesis, deep sub-micron process effects.
- Excellent analytical and debugging skills and the ability to proactively solve issues.
- Ability to guide others based on changing priorities.
- Proven ability to thrive on, learn and adapt to new methodologies and technologies.
- Good software and scripting skills; knowledge of synthesis, timing algorithms.
- Must be able to work autonomously while keeping management apprised of status.
- Be able to understand System Verilog, Verilog and VHDL languages.
- Excellent oral and written communications skills.
- Background in 28nm process or lower.
- Python/PERL/TCL language knowledge.
- Backgrounds on standard cell, layout, timing/power views, and characterization.
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