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Principal Engineer - ASIC Implementation
Job Location :
Northwest Region
Portland, Oregon
United States
Microchip
Northwest Region
450 Holger Way
San Jose, CA 95134
United States
Employment term : Full Time
Degree : Bachelors
Travel : Yes
Job level : Senior Level 7+ yrs.
Work Authorization :
  • Authorized to work
  • Microchip has an opportunity for a Principal ASIC Implementation Engineer at our office in Portland Oregon.  As a key member of Microchip's ASIC Implementation team, the successful candidate will take responsibility for a team of engineers to execute Microchip's ASIC development methodologies with a focus on top-level timing closure and/or synthesis.  They will coordinate the analysis and distribution of relevant timing information to sub-block/subsystem implementation engineers, as well as the Design and DFT groups.

    Working knowledge of system Verilog design and verification for common IP, top-level DFT insertion, macro level test structures for high-performance devices is essential.  The successful candidate will work closely with our internal and external customers to support them through Microchip's Chip development flow. They will also work with other Microchip groups across disciplines (CAD, Packaging, Mixed Signal, Operations, Layout) to facilitate the successful completion of the IC.  Microchip's Principal Engineers lead, manage and mentor engineers to ensure that they understand and adhere to flows using state-of-the art tools to build large and complex SOCs/ASICs.

    Responsibilities

    • Develop and execute implementation plans to synthesize, implement Design for Test, and/or close timing on complex digital integrated circuits at the block, subsystem or device level (1M to 1000M+ gates), which are coded in VHDL/Verilog/System Verilog.
    • Use metric-driven techniques to help ensure first-pass working silicon and provide regular, meaningful progress reports.
    • Create, enhance, and maintain synthesis, DFT, and Static Timing scripts to establish or update best-in-class methodologies. 
    • Analyze log and report files to ensure tools are properly configured to provide accurate results and make necessary adjustments to ensure that the manufactured device will function according to the design specification.
    • Mentor Senior/Junior team members and contractors on Chip-level and Macro-level ASIC design and implementation flows and processes.
    • Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems.
    • Provide technical support for internal and external ASIC customers to ensure the ASIC projects are successful as per the development plans.
    • Take responsibility for a team of engineers of varied experience and lead them to the successful implementation of a IC design within schedule constraints.

    Job Requirements

    Required

    • BSEE with 10-12 years of ASIC development experience in a fast-paced environment.
    • Design and Synthesis experience in high performance design (high speed / low power).
    • State of the art knowledge of semi-custom design implementation tools.
    • Experience with tools and methodologies for synthesis, hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization, and ECOs.
    • Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, 'physical aware' synthesis, deep sub-micron process effects.
    • Excellent analytical and debugging skills and the ability to proactively solve issues.
    • Ability to guide others based on changing priorities.
    • Proven ability to thrive on, learn and adapt to new methodologies and technologies.
    • Good software and scripting skills; knowledge of synthesis, timing algorithms.
    • Must be able to work autonomously while keeping management apprised of status.
    • Be able to understand System Verilog, Verilog and VHDL languages.
    • Excellent oral and written communications skills.

     Preferred

    • Background in 28nm process or lower.
    • Python/PERL/TCL language knowledge.
    • Backgrounds on standard cell, layout, timing/power views, and characterization.

    *LI-CO1

    Equal Opportunity Employer

    Microchip is an Equal Opportunity/Affirmative Action Employer of Disabled / Veterans / Minorities / Women. We provide equal employment and affirmative action opportunities to applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other basis protected under applicable federal, state or local laws.

    For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.

    Applicants with Disabilities

    If you need accommodation for any part of the employment process because of a medical condition or disability, please send us an email here with "Applicant Accommodation Request" in the subject line of the email. Alternatively, you may call us at 480-730-7330 to let us know the nature of your request.


    Microchip Profile:

    Microchip Technology Inc. The Embedded Control Solutions Company®

    Microchip Technology Inc. is a leading provider of microcontroller and analog semiconductors, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.

    Microchip's Quality System is based on the elements and criteria specified by ISO/TS-16949. ISO/TS-16949 is the highest quality system certification mandated by the world's major automotive customers. The specified controls apply to all stages of design and manufacturing.

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