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Senior Physical Design/Layout Engineer
Job Location :

EAST COAST, California
United States





EDA Careers
San Jose, CA 95119
United States
Employment term : Full Time
Degree : Bachelors
Travel : None
Job level : Mid Level 2-6 yrs.
Work Authorization :
  • USA: Citizen
  • USA: Green Card holder
  • My client is a fast-growing fabless manufacturer of analog and mixed signal IC solutions, providing full turnkey custom ASIC development and manufacturing supply chain services. Their technology solutions enable them to quickly adapt to their customer’s ever evolving requirements. They ARE NOT a design services company, rather they are an adaptable custom ASIC solution provider.

    In addition to custom ASICs, they offer standard products targeting broad markets, specializing in Analog Front End SOICs (System On Integrated Circuit). communications and audio applications, augmented and virtual reality, and so much more.

    We are looking for the following types of engineers…All East Coast (North Carolina based) …Green card or Citizens only.  Relocation package offered plus healthy benefits.

    Layout Engineer #5339

    This Physical Design or Layout/Mask Design Engineer will work closely with the IC design team on layout, floor planning and implementation, and play a critical ownership role in the company’s IC Design team. We would consider someone without the analog layout if you also OWNED TOP LEVEL floorplanning/routing/management/etc. You will be managing the top level floor plan throughout the development, pad rind (or pins) power/ground routing, block to block routing, top level physical verification (LVS/DRC/ERC/ coverage etc. checks.), TO process, and then some lower level analog layout and routing.

    In this position you will proactively be ready (for ex.) if a block comes in large, you will catch it, raise the flag, allowing for the necessary adjustments. You will know (for ex) that there are 150 routes down this channel and have/make enough room for it up front or make the necessary adjustments, so caught early in the process.

    Tasks/responsibilities include: Block level layout up to top-level chip assembly – Physical Implementation of the product - -Verification including DRC, LVS, and ERC - Support parasitic extraction and analysis - Drive continued improvement of layout practices and procedures – Manage tape out flows – Liaison with fab houses

    Requirements: (Some combination of)

    • 6+ years’ experience in full-custom mixed-signal IC layout
    • Thorough understanding of EDA tools from Cadence, Mentor, and Synopsys
    • Standard cell development or knowledge of structured, pitched, or arrayed layout
    • Knowledge of performance analog and high-power layout techniques
    • Experience exercising and debugging IC verification flows (DRC, LVS, XOR, PEX)
    • Demonstrated experience in successful tapeouts of production IC’s
    • Written and verbal communication of requirements
    • Working with various routers (company has a proprietary router)

    Proficiency with SKILL and PCELL development – Standard cell -Working knowledge of Python, Perl, and/or Tcl, a plus

    Open to relocation

    Citizens and green Card holders only please

    For more information email or call 305-598-2222x1


    EDA Careers Profile:

    EDA-CAREERS is a unique company in the world of recruiting. With over 15 years in recruiting exclusively in the EDA/Semiconductor industry, we pride ourselves on our relationships. We WORK to help find the best fits for our companies and the best opportunities for our candidates. In effect, we become PARTNERS, so that both the candidate and the company process goes smoothly from beginning to end. That is why we have worked with over One Hundred companies in EDA, and placed such a broad array of candidates.  We do it all...R&D, AE's, Sales and Marketing.  We help virtually every level of talent and work Globally.

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