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Senior Application Engineer Formal Verification
Job Location :
California or Austin, California 95119
United States





EDA Careers
San Jose, CA 95119
United States
Employment term : Full Time
Degree : Masters
Travel : Yes
Job level : Mid Level 2-6 yrs.
Work Authorization :
  • USA: Citizen
  • USA: Green Card holder
  • Senior Field Applications Engineer...California-Austin but other locations considered ... Req # 5489

    My client is a leader in Verification and simply a great company; they treat their people well. Their software tools help companies to build extraordinarily reliable chips, that help the world's most innovative companies to create bug-free digital integrated circuits. They are pioneers of advanced formal techniques to solve practical verification challenges. Their focus is on formal verification of chip designs and they provide unique, award winning solutions for tough problems.


    The right candidate will do Presales and some Post–sales support. They must have strong customer facing skills and own the technical side of the customer relationship, helping the company develop their product. Technically, you will help to enable customers to apply property checking solutions for Formal and Functional Verification of complex modules, IP, processors, and sub-systems, as well as equivalence checking solutions for synthesis and verification for ASIC and FPGA designs. 

    You will create and perform technical presentations and demonstrations at customer site, and drive and manage technical evaluations. You are someone who is/was an FAE from one of the other formal teams or a heavy user of formal – not someone who does UVM and has seen formal and ran connectivity once, but a real user of formal. 


    The successful candidate will possess the following combination of education and experience: Master’s degree (or PhD) in electrical engineering, microelectronics, computer science or physics and have 4+ years of relevant experience in formal verification of digital circuits, (a prerequisite). (Since they have several openings at various levels, experience can vary). Knowledge of verification languages (SVA, PSL), verification methodologies and tools. Working knowledge of HDL such as Verilog, SystemVerilog, and VHDL required.

    Strong communication skills to interact with external customers and internal engineering staff.

    Must have hands-on Formal experience with any of the commercial formal tools such as Jasper, OneSpin, Mentor Questa, DC-Formal or VC-Formal

     The right candidate should have significant proven relationships with several major well-respected customers and established contacts within. 

    Green card or Citizen required…no H-1’s please.

    For more information email or call 305-598-2222x1

    EDA Careers Profile:

    EDA-CAREERS is a unique company in the world of recruiting. With over 15 years in recruiting exclusively in the EDA/Semiconductor industry, we pride ourselves on our relationships. We WORK to help find the best fits for our companies and the best opportunities for our candidates. In effect, we become PARTNERS, so that both the candidate and the company process goes smoothly from beginning to end. That is why we have worked with over One Hundred companies in EDA, and placed such a broad array of candidates.  We do it all...R&D, AE's, Sales and Marketing.  We help virtually every level of talent and work Globally.

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