Microchip has an opportunity for a Principal ASIC Implementation Engineer at our office in Portland Oregon. As a key member of Microchip's ASIC Implementation team, the successful candidate will take responsibility for a team of engineers to execute Microchip's ASIC development methodologies with a focus on top-level timing closure and/or synthesis. They will coordinate the analysis and distribution of relevant timing information to sub-block/subsystem implementation engineers, as well as the Design and DFT groups.
Working knowledge of system Verilog design and verification for common IP, top-level DFT insertion, macro level test structures for high-performance devices is essential. The successful candidate will work closely with our internal and external customers to support them through Microchip's Chip development flow. They will also work with other Microchip groups across disciplines (CAD, Packaging, Mixed Signal, Operations, Layout) to facilitate the successful completion of the IC. Microchip's Principal Engineers lead, manage and mentor engineers to ensure that they understand and adhere to flows using state-of-the art tools to build large and complex SOCs/ASICs.
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