My client is a fast growing stable company in need of a Section Lead, Analog Design Manager as well as more junior Analog Designers, not interns please. This opportunity gives responsibility for the development of analog or mixed-signal CMOS IP that will be integrated into via-configurable arrays. This Technical Manager in HANDS-ON and knows (virtually) everything about Analog design, and can also manage a few engineers in the group.
Analog transistor/gate level design and simulation, behavioral modeling of IP, physical layout/verification, and lab evaluation.
(Spectre Cadence based AMSIM Spectre, either/or)
Physical layout experience - Wide breadth of analog or mixed-signal block design- Background in Verilog-A Verilog/VHDL - Coding experience
Preferences: MSEE degree Physical layout experience - Wide breadth of analog block design- Background in Verilog-A Verilog/VHDL - Coding experience
For more information email firstname.lastname@example.org or call 305-598-2222x1