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Subject:	Qualcomm is looking for a SoC Physical Design Engineer

Hello there.<BR><BR>
I was looking at TechJobsCafe.com and noticed an opportunity you might be interested in.<BR><BR>
<B>Qualcomm</B> currently has an open position for a <a href='https://www.techjobscafe.com/job_tracker.php?job_id=8966' title='This link will take you to the SoC Physical Design Engineer job application on TechJobsCafe.com'>SoC Physical Design Engineer</a>. <BR>
Here is the job description:<BR>
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<p>As a Physical Design Engineer, you will work with microarchitecture, RTL design and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.</p>
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<p><strong>Roles and Responsibilities </strong></p>
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<li>Perform block level implementation using place and route techniques to meet area/timing and power requirements</li>
<li>Create floorplan with pin placement, partitions and power grid</li>
<li>Generate block level static timing constraints</li>
<li>Perform Synthesis, Place & Route on the designs using industry standard tools and deliver GDS</li>
<li>Validate the designs for functional and electrical robustness</li>
<li>Generate and implement ECOs to fix noise, timing and EM/IR violations</li>
<li>Involve in defining correct by construction physical design methodologies.</li>
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<div>Additional Job Description</div>
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<p><strong>Preferred qualifications </strong></p>
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<li>MS degree in Electrical Engineering; 10 years of practical experience</li>
<li>Experience in developing and implementing power grid and clock specifications</li>
<li>Experience in all aspects of timing closure for multi-clock domain designs</li>
<li>Experience in deep submicron process technology nodes is strongly preferred</li>
<li>Knowledge of library cells and optimizations</li>
<li>Solid understanding industry standard tools for synthesis, place & route and tapeout flows</li>
<li>Solid understanding of physical design verification methods to debug LVS/DRC.</li>
<li>Experience with Synthesis, place and route and signoff timing/power analysis</li>
<li>Knowledge of all aspects of physical construction, integration, physical and electrical verification</li>
<li>Knowledge of basic SoC architecture and HDL languages like Verilog.</li>
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<p><strong>Physical Requirements </strong></p>
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<p>Frequently transports between offices, buildings, and campuses up to ½ mile.</p>
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<p>Frequently transports and installs equipment up to 5 lbs.</p>
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<p>Performs required tasks at various heights (e.g., standing or sitting).</p>
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<p>Monitors and utilizes computers and test equipment for more than 6 hours a day.</p>
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<p>Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.</p>
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<p><strong>Applicants </strong>: If you are an individual with a disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm is an equal opportunity employer and supports workforce diversity.</p>
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</div><BR><BR><a href='http://www.techjobscafe.com/job_tracker.php?job_id=8966'>For more information or if you want to apply, follow this link</a>, or cut and paste the following link to your Internet Browser https://www.techjobscafe.com/job_tracker.php?job_id=8966.<BR>
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